The present invention relates to a liquid crystal display device of an active matrix type, and more particularly to a structure of a driving substrate formed with a picture element, a thin film transistor, a capacitor element, etc.
In Japanese Patent Laid-open Publication No. 1-81262, there is disclosed an active matrix substrate having a large capacity in a liquid crystal picture element section without reducing an aperture ratio. FIG. 39 shows a structure of such a capacitor for a thin film transistor (TFT) formed on the active matrix substrate. Referring to FIG. 39, a recess (trench) 2 is formed on a quartz substrate 1. A first polysilicon layer 3 is formed on an inner surface of the trench 2, and a second polysilicon layer 6 is formed so as to be opposed to the first polysilicon layer 3 with a silicon oxide insulating film 4a and a silicon nitride insulating film 5a sandwiched therebetween, thus forming the capacitor (trench capacitor). On the other hand, a third polysilicon layer 7 is formed as a semiconductor layer of the TFT on the quartz substrate 1, and a fourth polysilicon gate electrode 8 is formed on the semiconductor layer through a silicon oxide gate insulating film 4b and a silicon nitride gate insulating film 5b. The TFT further includes an indium tin oxide (ITO) electrode 9 and an aluminum or silicon electrode 10. Reference numerals 11, 12 and 13 designate a first interlayer insulating film, a second interlayer insulating film and a passivation film, respectively.
In the above structure, the first polysilicon layer 3 of the trench capacitor is formed not integrally with the third polysilicon layer 7 of the TFT, but it is necessary to form a contact portion for connecting the first polysilicon layer 3 to the third polysilicon layer 7 as shown by a width W in FIG. 39. Accordingly, an occupied area W.sup.2 of the contact portion is necessary. Actually, the width W is about 5 .mu.m, and accordingly the occupied area W.sup.2 becomes about 25 .mu.m.sup.2. As a result, an aperture ratio is unavoidably reduced. Further, the contact portion for connecting the capacitor and the TFT is apt to have a multilayer structure and many steps, causing disconnection of an aluminum wiring or the like.
FIG. 40 shows a general equivalent circuit of an active matrix type liquid crystal display device. As shown in FIG. 40, m gate lines (G.sub.1 to G.sub.m) and n source lines (S.sub.1 to S.sub.n) are so arranged as to intersect each other at right angles. At each intersection of the gate lines and the source lines, there are formed a thin film transistor (MOS-FET) 201, a charge storing capacitor 202 as a capacitor element, and a liquid crystal cell 203 constituting a picture element. The active matrix type liquid crystal display device having such a structure is driven in the following manner. That is, a scanning signal having a pulse width set to one horizontal scanning period is sequentially applied to the gate lines G.sub.1 to G.sub.m. During the period of selection of one gate line, a sampled display signal is sequentially held in the source lines S.sub.1 to S.sub.n. Immediately thereafter, the display signal is written into the corresponding picture element. The display signal written into the picture element is held for one field period by the liquid crystal cell 203 and the capacitor 202, and it is then rewritten to a signal reversed in polarity in the next field. Thus, alternating-current drive of the liquid crystal is effected.
The larger a picture element capacity of each liquid crystal cell 203, the more securely a picture element potential can be held, so that nonuniformity of contrast can be suppressed to thereby secure a fixed display quality. Accordingly, in the case that a picture element electrode area is large (e.g., 200.sup.2 .mu.m.sup.2 or more), it is unnecessary to especially provide the capacitor element. However, in the case that a picture element is made small or very small in a small-sized display device, the picture element electrode area becomes remarkably small (e.g., 100.sup.2 .mu.m.sup.2 or less), and the capacitor element is therefore essential to compensate for the picture element capacity.
In general, the capacitor element is required to have a capacity about five times the picture element capacity in order to ensure stable sampling and holding of the display signal. Generally, the capacitor element has a MOS structure, and it is formed on a flat surface of a substrate. To ensure a necessary capacity, it is necessary to enlarge an electrode area. Accordingly, in the case that the picture element is made small, an area occupation ratio of the capacitor electrode is increased to cause a reduction in aperture ratio (i.e., a ratio of a picture element electrode area to a display area). Particularly in the case that the picture element electrode area is 50.sup.2 .mu.m.sup.2 or less, the aperture ratio is greatly reduced.
As a solution for the above problem, the use of a so-called trench type capacitor element is known in Japanese Patent Laid-open Publication No. 1-81262, for example. FIG. 41 shows a structure of such a trench type capacitor element in section. As shown in FIG. 41, a recess or trench 205 is formed on an upper surface of a quartz substrate 204. A laminated structure consisting of a first electrode film 206, a dielectric film 207 and a second electrode film 208 is formed on an inner wall of the trench 205 to constitute a so-called trench capacitor element 209. As apparent from the drawing, an effective area of the electrode films 206 and 208 is larger than a plane opening area of the trench 205, and a capacitance can therefore be increased without enlarging a size of the capacitor element. Accordingly, the use of the trench capacitor element 209 can suppress the area occupation ratio of the capacitor electrode to thereby achieve a desired aperture ratio even in the case of a very small picture element. On the other hand, a planar thin film transistor 210 is formed on a flat upper surface of the substrate 204. That is, a polycrystal silicon thin film 211 constituting a semiconductor region of the transistor 210 is formed on the substrate 204. Further, two layers of gate insulating films 212 and 213 are formed on the semiconductor region, and a gate electrode 214 is formed on the two layers. Further, a picture element electrode 216 is electrically connected through an interlayer insulating film 215 to a drain region of the transistor 210, and an electrode 217 connected to a source line is electrically connected through the interlayer insulating film 215 to a source region of the transistor 210. These laminated structures are covered with a passivation film 218.
In the prior art shown in FIG. 41, the capacitor element is formed in a trench structure to aim at reduction in planar size. However, the thin film transistor is of a planar type. It is considered that the aperture ratio of the picture element may be further improved by reducing the planar size of the transistor element. From this viewpoint, the present applicant has proposed that not only the capacitor element but also the thin film transistor be formed in a trench structure. FIG. 42 schematically shows such a trench structure in cross section. It is to be noted that the structure shown in FIG. 42 does not pertain to the prior art, but it is intended to be shown by way of reference for easy understanding of the present invention. As shown in FIG. 42, a thin film transistor 220 is formed by utilizing a trench 221. On an inner wall surface of the trench 221, there are formed a first polysilicon layer 222 constituting a semiconductor region, a gate insulating film 223, and a second polysilicon layer 224 constituting a gate electrode in such a manner as to fill the trench 221. A in electrode 226 is connected through a first interlayer insulating film 225 to a source region of the transistor 220. The in electrode 226 is connected to a source line. Further, a picture element electrode 227 is connected through the first interlayer insulating film 225 to a drain region of the transistor 220. An upper surface of the transistor 220 is covered with a second interlayer insulating film 228.
Similarly, a capacitor element 230 has a trench structure. That is, the first polysilicon layer 222 constituting a first electrode, the dielectric or insulating film 223 and the second polysilicon layer 224 as a second electrode are formed on an inner wall surface of a trench 231. Further, the first interlayer insulating film 225 and the second interlayer insulating film 228 are laminated on the trench structure of the capacitor element.
The trench structure of the thin film transistor 220 enables a small size of the transistor, especially, a gate length thereof to be reduced. Accordingly, the fineness of a thin film transistor can be accelerated to achieve a small size of not only a transistor for switching a picture element but also a transistor to be used in a peripheral circuit, thereby effecting high integration of a shift register or the like. Further, as an effective three-dimensional gate length along the inner wall of the trench can be set to an ordinary size, an ordinary supply voltage level can be used. Further, while an apparent two-dimensional gate length is reduced, no measures against a so-called short channel effect or the like are necessary because the actual three-dimensional gate length can be set to the ordinary size. In addition, since an upper surface of the trench element is superior in flatness, honing for control of liquid crystal molecule orientation can be uniformly performed. Accordingly, a region where the trench element is formed need not be shielded especially by a black mask or the like, but can be utilized as an aperture.
FIG. 43 is an enlarged section view showing a shape of the trench 221 for forming the thin film transistor 220 shown in FIG. 42. In general, the trench 221 has vertical side walls. The first polysilicon layer 222 is so deposited as to continuously cover an upper surface of a substrate 240, the vertical side walls of the trench 221 and a bottom surface of the trench 221. Since the first polysilicon layer 222 is used as the semiconductor region of the transistor 220, a solid-phase growth process for increasing a polysilicon crystal grain size is necessary. If the solid-phase growth process is not performed, desired current drive characteristics to be demanded by the transistor cannot be obtained, so that there occurs variations in Ion/Ioff characteristic and Vth characteristic, for example. In performing the solid-phase growth process, it is necessary to implant silicon ions (Si.sup.+) into an upper surface of the first polysilicon layer 222 prior to heating. However, as ion implantation of the silicon ions has anisotropy, a portion of the first polysilicon layer 222 deposited on the vertical side walls of the trench 221 becomes a shadow portion 241 in the process of ion implantation, causing nonuniformity of the solid-phase growth. In addition, a so-called step coverage at perpendicular step portions 242 occurs to cause frequent disconnection of the first polysilicon layer 222.
In the prior art shown in FIG. 41, the trench 205 is formed on the upper surface of the insulating substrate 204 which is formed of quartz or the like. In general, the formation of the trench 205 is effected by utilizing plasma etching or the like. FIG. 44 shows a process of forming such a trench. As shown in FIG. 44, a patterned resist 419 is first formed on an upper surface of a quartz insulating substrate 404, and then reactive plasma is irradiated through an opening 420 of the resist 419 to the substrate 404, thereby partially removing the quartz to form a trench 405. In general, the trench 405 is required to have a depth of about 3 .mu.m, so as to form a capacitor element therein. However, a selection ratio of the resist 419 to the insulating substrate 404 in the etching process (i.e., a ratio of an etching rate of the insulating substrate 404 to an etching rate of the resist 419) cannot be made high. That is, the insulating substrate 404 formed of quartz has a dense fine structure, and the resist 419 formed of an organic material has a structure not durable against a long-term etching process. For example, at the time the insulating substrate 404 is etched to a depth of about 1 .mu.m, the resist 419 is entirely etched off to disappear. Accordingly, in order to obtain a target trench depth of 3 .mu.m, the formation of the resist 419 and the etching process must be repeated which reduces the production efficiency.